The LVDS and OCT standards are widely accepted among I/O standards that support high data rates in electronic and opto-electronic systems. LVDS has been used in applications that require low voltage, high speed, low noise, low power, and lower electromagnetic interference. In addition, LVDS supports the high data throughput necessary for high-speed interfaces such as those in backplane circuits. LVDS compliant I/O interfaces have several advantages compared to other known interface levels, including differential signals with good noise margin and compatibility over different supply voltage levels, etc. But LVDS interfaces need precise line termination resistors.
OCT compliant I/O interfaces include series, parallel, and/or differential terminations on chip, where OCT resisters are placed adjacent to I/O buffers to eliminate stub effect and to help prevent reflections. OCT provides the benefit of high signal integrity, simpler board design, lower cost systems and good system reliability. OCT also allows system designers to use fewer resistors, fewer board traces, smaller board space, and fewer excess components on printed circuit boards.
A common LVDS compliant I/O interface includes an I/O buffer and stacked transistors coupled in parallel with the I/O buffer. Since the same type of devices are typically used to form the stacked transistors and the I/O buffer, the LVDS stacked transistors are stressed at the same time as the I/O buffer during an ESD event.
OCT compliant I/O interfaces also have ESD issues because OCT transistors are often connected to the I/O pads. These OCT transistors are typically far narrower than the ones used in the I/O buffers. As such, the OCT transistors have even lower ESD threshold voltages than the transistors in the I/O buffers.
Therefore, there is a need for improved ESD protection for the LVDS and OCT compliant interface circuits.